The variation of drive current in transistor circuits due to various parameters such as temperature, gate length or threshold voltage sometimes leads to undesirable compromise in circuit performance. U.S. Pat. application No. 837,200, filed Feb. 14, 1992 and assigned to Texas Instruments, INC. addresses the temperature compensation generally needed in a circuit involving transistors. Metal oxide semiconductor ("MOS") circuits and complementary metal oxide semiconductor ("CMOS") circuits have operating characteristics which are strongly dependent upon parameters such as gate length, threshold voltage, or temperature. In particular, the conductance of MOS or of a CMOS field effect transistor ("FET") decreases with increasing temperature. As a result of this variation, circuit performance must sometimes be reduced to keep a circuit functional over a reasonable temperature range. FET performance is generally reduced so that the transistor will not over-conduct in the low temperature domain. This compromise results in a less capable circuit given a particular level of technology. In most instances, a circuit designed to operate over a wide temperature range simply does not switch as fast as a circuit designed to operate over a narrow temperature range.
Over-conductance in FET circuits causes a momentarily high rate of current change per unit time through the FET when the FET turns on. This change, when coupled with the inherent inductance of a circuit, causes an induced electromotive force ("EMF") which opposes the flow of current. This induced EMF will create a noise in the voltage supply and ground plane. This in turn may cause various errors known in the art such as clock cycle failure. A circuit designed not to cause such errors at low temperature may be slower than would otherwise be necessary at high temperature.
It is sometimes desired to introduce a delay in a circuit of a magnitude equal or greater than some given delay, for example to allow for a specified amount of skew in input signals. A circuit with delay designed to meet that requirement at low temperature may be slower than otherwise necessary at high temperature. Therefore, a need has arisen for a circuit for MOS and CMOS applications which is able to compensate for parameter induced conductance variation.